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CD4066BC Quad Bilateral Switch
November 1983 Revised October 2005
CD4066BC Quad Bilateral Switch
General Description
The CD4066BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4016BC, but has a much lower "ON" resistance, and "ON" resistance is relatively constant over the input-signal range. s High degree linearity High degree linearity High degree linearity s Extremely low "OFF" 0.1% distortion (typ.) @ fis = 1 kHz, Vis = 5Vp-p, VDD-VSS = 10V, RL = 10 k 0.1 nA (typ.) 1012(typ.)
switch leakage: @ VDD-VSS = 10V, TA = 25C s Extremely high control input impedance s Low crosstalk
Features
s Wide supply voltage range s High noise immunity analog switching s "ON" resistance for 15V operation 80 s Matched "ON" resistance over 15V signal input s "ON" resistance flat over peak-to-peak signal range s High "ON"/"OFF" 65 dB (typ.) @ fis = 10 kHz, RL = 10 k output voltage ratio s Control Line Biasing: Switch On (Logic 1), VC = VDD Switch Off (Logic 0), VC = VSS s Wide range of digital and 3V to 15V 0.45 VDD (typ.)
-50 dB (typ.)
@ fis = 0.9 MHz, RL = 1 k
between switches
s Frequency response, switch "ON" 40 MHz (typ.)
7.5 VPEAK
Applications
* Analog signal switching/multiplexing * Signal gating * Squelch control * Chopper * Modulator/Demodulator * Commutating switch * Digital signal switching/multiplexing * CMOS logic implementation * Analog-to-digital/digital-to-analog conversion * Digital control of frequency, impedance, phase, and analog-signal-gain
RON = 5 (typ.)
Ordering Code:
Order Number CD4066BCM CD4066BCSJ CD4066BCN Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Schematic Diagram
(c) 2005 Fairchild Semiconductor Corporation
DS005665
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CD4066BC
Absolute Maximum Ratings
(Note 1) (Note 2) Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 300C (Note 2) 700 mW 500 mW
Recommended Operating Conditions (Note 2)
Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3V to 15V 0V to VDD
-0.5V to +18V -0.5V to VCC+0.5V -65C to +150C
-55C to +125C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current VDD = 5V VDD = 10V VDD = 15V SIGNAL INPUTS AND OUTPUTS RON "ON" Resistance
Conditions
-55C Min Max 0.25 0.5 1.0 Min
+25C Typ 0.01 0.01 0.01 Max 0.25 0.5 1.0
+125C Min Max 7.5 15 30
Units
A
RL = 10 k to (VDD - VSS/2) VC = VDD, V SS to VDD VDD = 5V VDD = 10V VDD = 15V 800 310 200 270 120 80 1050 400 240 1300 550 320
RON
"ON" Resistance Between Any 2 of 4 Switches
RL = 10 k to (VDD - VSS/2) VCC = V DD, VIS = VSS to VDD VDD = 10V VDD = 15V 10 5 50 0.1 50 500 nA
IIS
Input or Output Leakage Switch "OFF"
VC = 0
CONTROL INPUTS VILC LOW Level Input Voltage VIS = V SS and VDD VOS = V DD and VSS IIS = 10A VDD = 5V VDD = 10V VDD = 15V VIHC HIGH Level Input Voltage IIN Input Current VDD = 5V VDD = 10V (Note 7) VDD = 15V VDD-VSS = 15V VDDVISV SS VDDVCV SS 3.5 7.0 11.0 -0.1 0.1 1.5 3.0 4.0 3.5 7.0 11.0 2.25 4.5 6.75 2.75 5.5 8.25 -10-5 10-5 -0.1 0.1 1.5 3.0 4.0 3.5 7.0 11.0 -0.1 0.1 A V 1.5 3.0 4.0 V
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CD4066BC
AC Electrical Characteristics
Symbol tPHL, tPLH Parameter Propagation Delay Time Signal Input to Signal Output
(Note 3)
Conditions Min Typ Max Units
TA = 25C, tr = tf = 20 ns and VSS = 0V unless otherwise noted VC = VDD, CL = 50 pF, (Figure 1) RL = 200k VDD = 5V VDD = 10V VDD = 15V tPZH, tPZL Propagation Delay Time Control Input to Signal Output High Impedance to Logical Level tPHZ, tPLZ Propagation Delay Time Control Input to Signal Output Logical Level to High Impedance Sine Wave Distortion Frequency Response-Switch "ON" (Frequency at -3 dB) RL = 1.0 k, CL = 50 pF, (Figure 2, Figure 3) VDD = 5V VDD = 10V VDD = 15V RL = 1.0 k, CL = 50 pF, (Figure 2, Figure 3) VDD = 5V VDD = 10V VDD = 15V VC = VDD = 5V, VSS = -5V RL = 10 k, VIS = 5Vp-p, f= 1 kHz, (Figure 4) VC = VDD = 5V, VSS = -5V, RL = 1 k, VIS = 5Vp-p, 20 Log10 VOS/VOS (1 kHz)-dB, (Figure 4) Feedthrough -- Switch "OFF" (Frequency at -50 dB) Crosstalk Between Any Two Switches (Frequency at -50 dB) Crosstalk; Control Input to Signal Output Maximum Control Input VDD = 5.0V, VCC = VSS = -5.0V, RL = 1 k, VIS = 5.0Vp-p, 20 Log10, VOS/VIS = -50 dB, (Figure 4) VDD = VC(A) = 5.0V; VSS = VC(B) = 5.0V, RL1 k, VIS(A) = 5.0 Vp-p, 20 Log10, VOS(B)/VIS(A) = -50 dB (Figure 5) VDD = 10V, RL = 10 k, RIN = 1.0 k, VCC = 10V Square Wave, CL = 50 pF (Figure 6) RL = 1.0 k, CL = 50 pF, (Figure 7) VOS(f) = 1/2 VOS(1.0 kHz) VDD = 5.0V VDD = 10V VDD = 15V CIS COS CIOS CIN Signal Input Capacitance Signal Output Capacitance Feedthrough Capacitance Control Input Capacitance VDD = 10V VC = 0V 6.0 8.0 8.5 8.0 8.0 0.5 5.0 7.5 MHz MHz MHz pF pF pF pF 150 mVp-p 0.9 MHz 1.25 40 MHz 0.1 125 60 50 ns ns ns % 125 60 50 ns ns ns 25 15 10 55 35 25 ns ns ns
Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: These devices should not be connected to circuits with the power "ON". Note 5: In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in CL wherever it is specified. Note 6: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input. Note 7: Conditions for VIHC: a) VIS = VDD, IOS = standard B series IOH b) VIS = 0V, IOL = standard B series IOL.
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CD4066BC
Typical Performance Characteristics
"ON" Resistance vs Signal Voltage for TA = 25C "ON" Resistance as a Function of Temperature for VDD-VSS = 15V
"ON" Resistance as a Function of Temperature for VDD-VSS = 10V
"ON" Resistance as a Function of Temperature for VDD-VSS = 5V
Special Considerations
In applications where separate power sources are used to drive VDD and the signal input, the VDD current capability should exceed VDD/RL (RL = effective external load of the 4 CD4066BC bilateral switches). This provision avoids any permanent current flow or clamp action of the VDD supply when power is applied or removed from CD4066BC. In certain applications, the external load-resistor current may include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8 or 11, the voltage drop across the bidirectional switch must not exceed 0.6V at TA 25C, or 0.4V at TA > 25C (calculated from RON values shown). No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9 or 10.
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CD4066BC
AC Test Circuits and Switching Time Waveforms
FIGURE 1. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 2. tPZH, tPHZ Propagation Delay Time Control to Signal Output
FIGURE 3. tPZL, tPLZ Propagation Delay Time Control to Signal Output
VC = VDD for distortion and frequency response tests VC = VSS for feedthrough test
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
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CD4066BC
AC Test Circuits and Switching Time Waveforms
(Continued)
FIGURE 5. Crosstalk Between Any Two Switches
FIGURE 6. Crosstalk: Control Input to Signal Output
FIGURE 7. Maximum Control Input Frequency
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CD4066BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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CD4066BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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CD4066BC Quad Bilateral Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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